`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/12/18 20:25:23
// Design Name: 
// Module Name: iir
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module IIR #(
    parameter DW = 10, EW = 4, STG = 2,
    parameter real GAIN[STG], real NUM[STG][3], real DEN[STG][2]
)(
    input wire clk, rst, en,
    input wire signed [DW-1 : 0] in,
    output logic signed [DW-1 : 0] out
);
    localparam W = EW + DW;
    logic signed [W-1 : 0] sio[STG+1];
    assign sio[0] = in, out = sio[STG];
    generate
        for(genvar s = 0; s < STG; s++) begin
            IIR2nd #(W, DW-1, GAIN[s], NUM[s], DEN[s]) theIir(clk, rst, en, sio[s], sio[s+1]);
        end
    endgenerate
endmodule
